| 1 |
A Comprehensive Reliability Assessment of
Fault-Resilient Network-on-Chip Using Analytical Model |
| 2 |
A Hardware-Software Co-designed AES-ECC Cryptosystem |
| 3 |
A Uniquified Virtualization Approach to
Hardware Security |
| 4 |
Clock-gating of streaming applications for energy
efficient implementations on FPGAs |
| 5 |
Compact
Constant Weight Coding Engines for the
Code Based Cryptography |
| 6 |
Construction of Rotation Symmetric S-Boxes
with High Nonlinearity and Improved DPA
Resistivity |
| 7 |
Classification of Error Correcting Codes and
Estimation of Interleaver Parameters in a
Noisy Transmission Environment |
| 8 |
Design and Applications for Embedded
Networks-on-Chip on FPGAs |
| 9 |
Overloaded CDMA Crossbar for Network-On-Chip |
| 10 |
Design and Validation for FPGA Trust under
Hardware Trojan Attacks |
| 11 |
High-Speed and Low-Latency ECC Processor
Implementation Over GF(2
m
)
on FPGA |
| 12 |
LAXY: A Location-Based Aging-Resilient
Xy-Yx Routing Algorithm for Network on Chip |
| 13 |
FoToNoC: A Folded Torus-Like
Network-on-Chip based Many-Core
Systems-on-Chip in the Dark Silicon Era |
| 14 |
Lightweight Hardware Architectures for the
Present Cipher in FPGA |
| 15 |
Multipartite entangled states, symmetric
matrices and error-correcting codes |
| 16 |
Designing an FPGA-Accelerated Homomorphic
Encryption Co-Processor |
| 17 |
VLIW Architecture |
| 18 |
Post-Quantum Cryptography on FPGA Based on
Isogenies on Elliptic Curves | | | | | | | | |
No comments:
Post a Comment