The
component’s failure in network-on-chips (NoCs) has been a critical
factor on the system’s reliability. In order to alleviate the impact of
faults, fault tolerance has been investigated in the recent years to
enhance NoC’s robustness. Due to the vast selection of fault-tolerance
mechanisms and critical design constraints, selecting and configuring an
appropriate mechanism to satisfy the fault-tolerance requirements
constitute new challenges for designers. Consequently, reliability
assessment has become prominent for the early stages of manufacturing
process to solve these problems. This paper approaches the
fault-tolerance analysis by providing an analytical model to approximate
the lifetime reliability and compares it with a system-level
simulation. Based on the proposed approach, we measure the
fault-tolerance efficiency using a new parameter, named reliability
acceleration factor. The goal of this paper is to provide an efficient
and accurate reliability assessment to help designers easily understand
and evaluate the advantages and drawbacks of their potential
fault-tolerance methods.
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