This
paper investigates the reduction of dynamic power for streaming
applications yielded by asynchronous dataflow designs by using clock
gating techniques. Streaming applications constitute a very broad class
of computing algorithms in areas such as signal processing, digital
media coding, cryptography, video analytics, network routing, packet
processing, etc. This paper introduces a set of techniques that,
considering the dynamic streaming behavior of algorithms, can achieve
power savings by selectively switching off parts of the circuits when
they are temporarily inactive. The techniques being independent from the
semantic of the application can be applied to any application and can
be integrated into the synthesis stage of a high-level dataflow design
flow. Experimental results of at-size applications synthesized on
field-programmable gate arrays platforms demonstrate power reductions
achievable with no loss in data throughput.
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