Monday, January 13, 2020

Online Voting System Using Android Device

Online Voting System Using Android Device

Android PHP Project


Voting plays a very important role in any democratic country .Voting is the system where citizens choose and replace government by doing elections. Hence these elections must be accurate and transparent. When elections are happening there is need for lot of man power for completion of elections properly and with desired security. Although lot of man power is used in elections there is no guarantee that elections will be done with no fake votes. Sometimes there are chances that fake votes can be done. Also for voting voter has to go to the voting booth and stand in line for long time. Due to this the percentage of voting reduced in some amount. Currently used voting system consumes much time and it is a very hectic process. Application for Online Voting System using Android Device (AOVSAD) provides the facility of casting votes without visiting the booth to the voters. The facial recognition secures the system by allowing the authentic voter for voting. One time password (OTP) provides another level of security to the system. To avoid fake voting and for providing voter an extra comfort by doing vote from remote place so that voter inspired to cast his vote and voting percentage will increase phenomenally. A new technique as Mobile based Facial Recognition can be implemented. This system provides extra bandwidth utilization for voting system.

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Friday, January 10, 2020

Iot Based Garbage Monıtorıng and Clearance Alert System

IotBased Garbage Monıtorıng and Clearance Alert System 
Code Shoppy Android Proejcts
Attributable to a change in perspective toward Internet of Things (IoT), inquires about into IoT administrations have been directed in an extensive variety of fields. As a noteworthy application field of IoT, squander administration has turned out to be one such issue. The nonappearance of proficient waste administration has caused genuine ecological issues and cost issues. In this way, in this paper, an IoT-based shrewd junk framework (SGS) is proposed to decrease the measure of nourishment squander. Code Shoppy In a SGS, battery-based shrewd rubbish canisters (SGBs) trade data with each other utilizing remote work systems, and a switch and server gather and break down the data for benefit provisioning. 
Moreover, the SGS incorporates different IoT systems thinking about client comfort and expands the battery lifetime through two sorts of vitality effective activities of the SGBs: remain solitary task and collaboration based activity. The proposed SGS had been worked as a pilot venture in Gangnam region, Seoul, Republic of Korea, for a one-year time span. The analysis demonstrated that the normal measure of nourishment waste could be lessened by 33%[1]. 
Garbage management is an issue of genuine worry in present day urban situation with exponentially rising populace. Aside from the need to diminish the expenses caused in trash administration, the region, in the meantime needs to guarantee a sheltered and solid condition for the subjects. This paper introduces the improvement of a cloud incorporated remote waste administration framework for keen urban areas. 
The proposed framework midway screens the temperature, dampness, combustible gases focuses, fire discovery and refuse fill volume in squander receptacles with the assistance of remote detecting hubs set at remote areas in the city. The correspondence from the sensor hub to the focal station is finished utilizing TCP/IP convention by means of existing GSM/GPRS remote framework in the city. At the cloud server, the information is observed, broke down and put away and notice to the specialist co-ops is sent for appropriate activity for flame avoidance and waste receptacle flood. The test results demonstrate that the proposed framework is a savvy and productive answer for squander administration in current urban situation.[2]. 
Commonly, in our city we see that the refuse containers or dustbins put at open places are over-burden. It makes unhygienicconditions for individuals and also offensiveness to that place leaving terrible stench. To keep away from every single such circumstance we will actualize a venture called IoT Based Smart Garbage and Waste Collection receptacles. These dustbins are interfaced with microcontroller based framework having IR remote frameworks alongside focal framework demonstrating current status of rubbish, on portable internet browser with html page by Wi-Fi.

Henceforth the status will be refreshed on to the html page. Significant piece of our venture relies on the working of the Wi-Fi module; fundamental for its execution. The principle point of this venture is to diminish HR and endeavors alongside the improvement of a shrewd city vision[3] Garbage monitoring is one of the essential issue that the world faces regardless of the instance of created or creating nation. The key issue in the waste administration is that the rubbish receptacle at open spots gets flooded well ahead of time before the initiation of the following cleaning process. It thus prompts different dangers, for example, awful smell and offensiveness to that place which might be the main driver for spread of different infections. To stay away from all such dangerous situation and keep up open tidiness and wellbeing this work is mounted on a shrewd rubbish framework.

Thursday, January 2, 2020

A Unified VLSI architecture for 1D IDCT and IDST based on pseudo-band correlations

A Unified VLSI architecture for 1D IDCT and IDST based on pseudo-band correlations


In this paper an efficient unified VLSI architecture for the computation of 1-D IDCT and IDST that have been reformulated to be implemented on the same hardware structure with a minimum modification is presented. The proposed design is based on a new unified VLSI algorithm that can be used to compute both transforms. Using the proposed algorithm an efficient VLSI architecture has been obtained based on the systolic array architectural paradigm with a low hardware complexity and a low number of I/O channels placed at the two ends of the linear array and having a low I/O bandwidth. Moreover the proposed architecture is modular, regular and with local connection favoring a good VLSI implementation.

Dis crete cosine transform (DCT) and discrete sine transform (DST) are basic functions used in many digital signal processing applications especially in video compression. It is well known that DCT offers better performances for high correlated images but for low correlated images DST gives better results. So, it is highly desirable to have a VLSI implementation for both transforms to be used in such applications. In real-time applications it is necessary to have efficient VLSI implementations for DCT and DST (forward and inverse) using FPGA or ASIC technology. It is well known that the efficiency of a VLSI implementation is given mainly not by the arithmetic complexity but by the communication one. So, it is necessary to restructure the algorithms or to derive new ones in order to obtain an efficient VLSI implementation[1]. 

Thus, the use of modular and regular computational structures (for example cycle convolution or circular correlations, but not only these) can be very useful for the VLSI implementation of DCT and inverse discrete cosine transform (IDCT) [2]-[10], DST or inverse discrete sine transform (IDST) [11]-[13], discrete Fourier transform (DFT) [14], or discrete Hartley transform (DHT) [15]-[18]. In this paper we propose an efficient VLSI implementation of both IDCT and IDST based on a modular and regular computational structure called pseudo-band correlation.

It is shown that it is possible to convert the computation of IDCT and IDST in a such computational structure and that can be obtained an efficient unified VLSI implementation with a high percentage of the chip area used by the both transforms. The rest of the paper is organized as follows: in Section II an unified VLSI algorithm based on a pseudo-correlation structure is proposed. In Section III it is presented the unified VLSI architecture

https://codeshoppy.com/android-projects-titles-ieee.html




THEUNIFIEDVLSIARCHITECTUREFOR1-DIDCT AND IDST

The hardware core for the proposed unified VLSI architecture for 1D IDCT and IDST is presented in Figure 1(a), whilst in Figure 1(b) there’s reflected the functionality of the processing elements(PE) of the proposed architecture, which has the purpose of selecting addition or subtraction depending on the case which is established by using the control bits dictated by sign. Equation (24) is the one that the hardware core is using for implementation, representing the pseudo-band correlation structure.
 
On this structure, the transform is mapped on a linear system array.The appropriate reorder of the auxiliary unified input and output sequences are obtained using the pre-processing and post-processing stages. 

The proposed unified algorithm is presented in (19) where in the pre-processing stage we compute the auxiliary input sequence {}1,...,1,0:)(−=NkkYuas shown in equation (26), and for the post-processing stage we recursively compute the auxiliary output sequence {}1,...,1,0:)(−=Nkkxby using (22) and (23). Equation (20) is the one that aids in controlling the sign of the output sequence. Based on the reformulated computation of 1-D IDST as a pseudo-band correlation used in [13], this paper presents a unified algorithm for IDCT and IDST, thus presenting the advantage of a better performance in digital signal processing applications for high and low correlated images. The IDCT transform can be thus implemented on a similar structure as that used for IDST, both having the same main core and modifications appearing in the pre-processing block.  Code Shoppy

Thus, the advantages include those presented in [13] which are small number of I/O channels located at the 2 extreme ends which aids in obtaining a highly efficient VLSI chip, low hardware costs, a high speed performance with low I/O costs. The unified VLSI architecture is highly regular, modular, with a reduced I/O bandwidth and a minimum hardware modification as both transform can be implemented on the same hardware structure with minimum adjustments.