In
this paper we report on our advances designing and implementing an
FPGA-based computation accelerator as part of a Homomorphic Encryption
Processing Unit (HEPU) co-processor. This hardware accelerator
technology improves the practicality of computing on encrypted data by
reducing the computational bottlenecks of lattice encryption primitives
that support homomorphic encryption schemes. We focus on accelerating
the Chinese Remainder Transform (CRT) and inverse Chinese Remainder
Transform (iCRT) for power-of-2 cyclotomic rings, but also accelerate
other basic ring arithmetic such as Ring Addition, Ring Subtraction and
Ring Multiplication. We instantiate this capability in a Xilinx Virtex-7
FPGA that can attach to a host computer through either a PCI-Express
port or Ethernet. We focus our experimental performance analysis on the
NTRU-based LTV Homomorphic Encryption scheme. This is a leveled
homomorphic encryption scheme, but our accelerator is compatible with
other lattice-based schemes and recent improved bootstrapping designs to
support arbitrary depth computation. We experimentally compare
performance with a reference software implementations of the CRT and
iCRT bottlenecks and when used in a practical application of encrypted
string comparison.
No comments:
Post a Comment