VLSI IEEE Projects Titles 2017 2018 

VLSI IEEE Projects Titles 2017 2018 

9790675343

contact@codeshoppy.com

 

S no	Title
1	A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model
2	A Hardware-Software Co-designed AES-ECC Cryptosystem
3	A Uniquified Virtualization Approach to Hardware Security
4	Clock-gating of streaming applications for energy efficient implementations on FPGAs
5	Compact Constant Weight Coding Engines for the Code Based Cryptography
6	Construction of Rotation Symmetric S-Boxes with High Nonlinearity and Improved DPA Resistivity
7	Classification of Error Correcting Codes and Estimation of Interleaver Parameters in a Noisy Transmission Environment
8	Design and Applications for Embedded Networks-on-Chip on FPGAs
9	Overloaded CDMA Crossbar for Network-On-Chip
10	Design and Validation for FPGA Trust under Hardware Trojan Attacks
11	High-Speed and Low-Latency ECC Processor Implementation Over GF(2 m ) on FPGA
12	LAXY: A Location-Based Aging-Resilient Xy-Yx Routing Algorithm for Network on Chip
13	FoToNoC: A Folded Torus-Like Network-on-Chip based Many-Core Systems-on-Chip in the Dark Silicon Era
14	Lightweight Hardware Architectures for the Present Cipher in FPGA
15	Multipartite entangled states, symmetric matrices and error-correcting codes
16	Designing an FPGA-Accelerated Homomorphic Encryption Co-Processor
17	VLIW Architecture
18	Post-Quantum Cryptography on FPGA Based on Isogenies on Elliptic Curves

Lightweight Hardware Architectures

In recent years, the study of lightweight symmetric ciphers has gained interest due to the increasing demand for security services in constrained computing environments, such as in the Internet of Things. However, when there are several algorithms to choose from and different implementation criteria and conditions, it becomes hard to select the most adequate security primitive for a specific application. This paper discusses the hardware implementations of Present, a standardized lightweight cipher called to overcome part of the security issues in extremely constrained environments. The most representative realizations of this cipher are reviewed and two novel designs are presented. Using the same implementation conditions, the two new proposals and three state-of-the-art designs are evaluated and compared, using area, performance, energy, and efficiency as metrics. From this wide experimental evaluation, to the best of our knowledge, new records are obtained in terms of implementation size and energy consumption. In particular, our designs result to be adequate in regards to energy-per-bit and throughput-per-slice.

 

VLSI IEEE Projects Titles 2017 2018  

9790675343

contact@codeshoppy.com

A Folded Torus-Like Network-on-Chi

Dark silicon refers to the phenomenon that a fraction of a many-core chip has to become “dark” or “dim” in order to guarantee the system to be kept in a safe temperature range and allowable power budget. Techniques have been developed to selectively activate non-adjacent cores on many-core chip to avoid temperature hotspot, while resulting unexpected increase of communication overhead due to the longer average distance between active cores, and in turn affecting application performance and energy efficiency, when Network-on-Chip (NoC) is used as a scalable communication subsystem. To address the brand-new challenges brought by dark silicon, in this paper, we present FoToNoC, a Folded Torus-like NoC, coupled with a hierarchical management strategy for heterogeneous many-core systems. On top of it, objectives of maximizing application performance, energy efficiency and chip reliability are isolated and well achieved by hardware-software co-design in several different phases, including application mapping and scheduling, cluster management and DVFS control. Evaluations on PARSEC benchmark applications demonstrate the significance of the entire strategy. Compared with state-of-the-art approaches, the proposed FoToNoC organization can achieve on average 35.4 and 35.2 percent on communication efficiency and application performance improvement, respectively, when maintaining the safe chip temperature. The hierarchical cluster-based management strategy can further reduce an average 34.6 percent of the total energy consumption with a notable reduction on the chip peak temperature. The significant achievements on system energy efficiency and the reduction on chip temperature of H.264 decoder and DSP-stone benchmarks additionally verify the effectiveness of the proposed methods.

 

VLSI IEEE Projects Titles 2017 2018  

9790675343

contact@codeshoppy.com

FPGA-Accelerated Encryption Co-Processor

In this paper we report on our advances designing and implementing an FPGA-based computation accelerator as part of a Homomorphic Encryption Processing Unit (HEPU) co-processor. This hardware accelerator technology improves the practicality of computing on encrypted data by reducing the computational bottlenecks of lattice encryption primitives that support homomorphic encryption schemes. We focus on accelerating the Chinese Remainder Transform (CRT) and inverse Chinese Remainder Transform (iCRT) for power-of-2 cyclotomic rings, but also accelerate other basic ring arithmetic such as Ring Addition, Ring Subtraction and Ring Multiplication. We instantiate this capability in a Xilinx Virtex-7 FPGA that can attach to a host computer through either a PCI-Express port or Ethernet. We focus our experimental performance analysis on the NTRU-based LTV Homomorphic Encryption scheme. This is a leveled homomorphic encryption scheme, but our accelerator is compatible with other lattice-based schemes and recent improved bootstrapping designs to support arbitrary depth computation. We experimentally compare performance with a reference software implementations of the CRT and iCRT bottlenecks and when used in a practical application of encrypted string comparison.

 

VLSI IEEE Projects Titles 2017 2018  

9790675343

contact@codeshoppy.com

Networks-on-Chip on FPGAs

Field-programmable gate-arrays (FPGAs) have evolved to include embedded memory, high-speed I/O interfaces and processors, making them both more efficient and easier-to-use for compute acceleration and networking applications. However, implementing on-chip communication is still a designer's burden wherein custom system-level buses are implemented using the fine-grained FPGA logic and interconnect fabric. Instead, we propose augmenting FPGAs with an embedded network-on-chip (NoC) to implement system-level communication. We design custom interfaces to connect a packet-switched NoC to the FPGA fabric and I/Os in a configurable and efficient way and then define the necessary conditions to implement common FPGA design styles with an embedded NoC. Four application case studies highlight the advantages of using an embedded NoC. We show that access latency to external memory can be ~1.5× lower. Our application case study with image compression shows that an embedded NoC improves frequency by 10-80%, reduces utilization of scarce long wires by 40% and makes design easier and more predictable. Additionally, we leverage the embedded NoC in creating a programmable Ethernet switch that can support up to 819 Gb/s-5× more switching bandwidth and 3× lower area compared to previous work. Finally, we design a 400 Gb/s NoC-based packet processor that is very flexible and more efficient than other FPGA-based packet processors.

 

VLSI IEEE Projects Titles 2017 2018  

9790675343

contact@codeshoppy.com

Design and Validation for FPGA Trust under

Field programmable gate arrays (FPGAs) are being increasingly used in a wide range of critical applications, including industrial, automotive, medical, and military systems. Since FPGA vendors are typically fabless, it is more economical to outsource device production to off-shore facilities. This introduces many opportunities for the insertion of malicious alterations of FPGA devices in the foundry, referred to as hardware Trojan attacks, that can cause logical and physical malfunctions during field operation. The vulnerability of these devices to hardware attacks raises serious security concerns regarding hardware and design assurance. In this paper, we present a taxonomy of FPGA-specific hardware Trojan attacks based on activation and payload characteristics along with Trojan models that can be inserted by an attacker. We also present an efficient Trojan detection method for FPGA based on a combined approach of logic-testing and side-channel analysis. Finally, we propose a novel design approach, referred to as Adapted Triple Modular Redundancy (ATMR), to reliably protect against Trojan circuits of varying forms in FPGA devices. We compare ATMR with the conventional TMR approach. The results demonstrate the advantages of ATMR over TMR with respect to power overhead, while maintaining the same or higher level of security and performances as TMR. Further improvement in overhead associated with ATMR is achieved by exploiting reconfiguration and time-sharing of resources.

 

VLSI IEEE Projects Titles 2017 2018  

9790675343

contact@codeshoppy.com

Construction of Rotation Symmetric S-Boxes

In this paper, we provide an n × n bijective rotation symmetric S-box (RSSB) construction with improved resistance to differential power analysis (DPA) using rotation-symmetric Boolean functions (RSBFs). The RSSB class is generated from an instance of a proposed RSSB construction and then iteratively applying a simulated annealing algorithm in the respective neighborhood of the RSSB followed by a hill climbing algorithm to obtain a good tradeoff of cryptographic properties. The constructed 8 × 8 RSSBs have a nonlinearity of 102 and transparency order value 7.709 whereas the Rijndael S-box has a higher transparency order of 7.86. The evaluation of security metric called guessing entropy on the constructed RSSBs shows that a side-channel adversary requires more effort to exploit information leakage from the simulated power traces. In comparison to Rijndael S-box, the correlation based DPA on RSSBs which when incorporated in AES-128, shows requirement of significantly more power traces when implemented on Xilinx Virtex-5 FPGA device on SASEBO-GII development board. While the distributed memory and block memory implementations of the Rijndael S-box required 500 and 2,000 power traces to extract the last round key, our proposed RSSBs required 2,000 and 12,000 power traces respectively.

 

VLSI IEEE Projects Titles 2017 2018  

9790675343

contact@codeshoppy.com

Constant Weight Coding Engines for the

We present here a more memory efficient method for encoding binary information into words of prescribed length and weight. Existing solutions either require complicated float point arithmetic or additional memory overhead, making it a challenge for resource constrained computing environment. The solution we propose here solves these problems yet obtains better coding efficiency by a memory efficient approximation of the critical intermediate value in constant weight coding. For the time being, the design presented in this brief is the most compact one for any code-based encryption schemes.

 

VLSI IEEE Projects Titles 2017 2018  

9790675343

contact@codeshoppy.com

Clock-gating of streaming applications for energy

This paper investigates the reduction of dynamic power for streaming applications yielded by asynchronous dataflow designs by using clock gating techniques. Streaming applications constitute a very broad class of computing algorithms in areas such as signal processing, digital media coding, cryptography, video analytics, network routing, packet processing, etc. This paper introduces a set of techniques that, considering the dynamic streaming behavior of algorithms, can achieve power savings by selectively switching off parts of the circuits when they are temporarily inactive. The techniques being independent from the semantic of the application can be applied to any application and can be integrated into the synthesis stage of a high-level dataflow design flow. Experimental results of at-size applications synthesized on field-programmable gate arrays platforms demonstrate power reductions achievable with no loss in data throughput.

 

VLSI IEEE Projects Titles 2017 2018  

9790675343

contact@codeshoppy.com

Error Correcting Codes

Channel encoder, which includes a forward error correcting (FEC) code followed by an interleaver, plays a vital role in improving the error performance of digital storage and communication systems. In most of the applications, the FEC code and interleaver parameters are known at the receiver to decode and de-interleave the information bits, respectively. But the blind/semi-blind estimation of code and interleaver parameters at the receiver will provide additional advantages in applications, such as adaptive modulation and coding, cognitive radio, non-cooperative systems, etc. The algorithms for the blind estimation of code parameters at the receiver had previously been proposed and investigated for known FEC codes. In this paper, we propose algorithms for the joint recognition of the type of FEC codes and interleaver parameters without knowing any information about the channel encoder. The proposed algorithm classify the incoming data symbols among block coded, convolutional coded, and uncoded symbols. Further, we suggest analytical and histogram approaches for setting the threshold value to perform code classification and parameter estimation. It is observed from the simulation results that the code classification and interleaver parameter estimation are performed successfully over erroneous channel conditions. The proposed histogram approach is more robust against the analytical approach for noisy transmission environment and system latency is one of the important challenges for the histogram approach to achieve better performance.

 

VLSI IEEE Projects Titles 2017 2018  

9790675343

contact@codeshoppy.com

Uniquified Virtualization Approach to Hardware Security

Virtualization has well-known security advantages for operating systems and software, but current techniques do not address increasingly important hardware-security concerns. For widely deployed systems (e.g., Internet of Things) and safety-critical systems (e.g., defense and automobiles), protecting against device tampering is critical, but is often unavoidable due to the relative ease of side-channel attacks. In this letter, we present a novel usage of virtualization that limits damage from bitstream tampering to a single instance of a deployed system by employing unique virtual architectures (i.e., overlays) on field-programmable gate arrays.

 

VLSI IEEE Projects Titles 2017 2018  

9790675343

contact@codeshoppy.com

Hardware-Software Co-designed AES

Securing data transfer is a primary need for all embedded systems. The AES-ECC hybrid cryptosystem combines advantages of the Advanced Encryption Standard (AES) to accelerate data encryption and the Elliptic Curve Cryptography (ECC) to secure the exchange of symmetric session key. In this paper, we present an improved AES-ECC system using a co-design approach where AES runs on NIOS II softcore and ECC's scalar multiplication is implemented as a hardware accelerator. The proposed system relies on optimizations of both AES (MixColumn/InvMiColumn operation) and ECC (Point Addition/Doubling layer). The implementation on a Cyclone IV FPGA uses 11% of total logic elements, 9% of total combinatorial functions and 7% of total memory. It runs at a frequency of 157.63 MHz and consumes 166.67 mW. A comparison with similar works shows that the proposed system provides an interesting trade-off between speed and area occupation.

 

VLSI IEEE Projects Titles 2017 2018  

9790675343

contact@codeshoppy.com

Network-on-Chip Using Analytical Model

The component’s failure in network-on-chips (NoCs) has been a critical factor on the system’s reliability. In order to alleviate the impact of faults, fault tolerance has been investigated in the recent years to enhance NoC’s robustness. Due to the vast selection of fault-tolerance mechanisms and critical design constraints, selecting and configuring an appropriate mechanism to satisfy the fault-tolerance requirements constitute new challenges for designers. Consequently, reliability assessment has become prominent for the early stages of manufacturing process to solve these problems. This paper approaches the fault-tolerance analysis by providing an analytical model to approximate the lifetime reliability and compares it with a system-level simulation. Based on the proposed approach, we measure the fault-tolerance efficiency using a new parameter, named reliability acceleration factor. The goal of this paper is to provide an efficient and accurate reliability assessment to help designers easily understand and evaluate the advantages and drawbacks of their potential fault-tolerance methods.

 

VLSI IEEE Projects Titles 2017 2018 

 9790675343

contact@codeshoppy.com