Securing
data transfer is a primary need for all embedded systems. The AES-ECC
hybrid cryptosystem combines advantages of the Advanced Encryption
Standard (AES) to accelerate data encryption and the Elliptic Curve
Cryptography (ECC) to secure the exchange of symmetric session key. In
this paper, we present an improved AES-ECC system using a co-design
approach where AES runs on NIOS II softcore and ECC's scalar
multiplication is implemented as a hardware accelerator. The proposed
system relies on optimizations of both AES (MixColumn/InvMiColumn
operation) and ECC (Point Addition/Doubling layer). The implementation
on a Cyclone IV FPGA uses 11% of total logic elements, 9% of total
combinatorial functions and 7% of total memory. It runs at a frequency
of 157.63 MHz and consumes 166.67 mW. A comparison with similar works
shows that the proposed system provides an interesting trade-off between
speed and area occupation.
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