A Unified VLSI architecture for 1D IDCT and IDST based on pseudo-band correlations

A Unified VLSI architecture for 1D IDCT and IDST based on pseudo-band correlations

In this paper an efficient unified VLSI architecture for the computation of 1-D IDCT and IDST that have been reformulated to be implemented on the same hardware structure with a minimum modification is presented. The proposed design is based on a new unified VLSI algorithm that can be used to compute both transforms. Using the proposed algorithm an efficient VLSI architecture has been obtained based on the systolic array architectural paradigm with a low hardware complexity and a low number of I/O channels placed at the two ends of the linear array and having a low I/O bandwidth. Moreover the proposed architecture is modular, regular and with local connection favoring a good VLSI implementation.

Dis crete cosine transform (DCT) and discrete sine transform (DST) are basic functions used in many digital signal processing applications especially in video compression. It is well known that DCT offers better performances for high correlated images but for low correlated images DST gives better results. So, it is highly desirable to have a VLSI implementation for both transforms to be used in such applications. In real-time applications it is necessary to have efficient VLSI implementations for DCT and DST (forward and inverse) using FPGA or ASIC technology. It is well known that the efficiency of a VLSI implementation is given mainly not by the arithmetic complexity but by the communication one. So, it is necessary to restructure the algorithms or to derive new ones in order to obtain an efficient VLSI implementation[1]. 

Thus, the use of modular and regular computational structures (for example cycle convolution or circular correlations, but not only these) can be very useful for the VLSI implementation of DCT and inverse discrete cosine transform (IDCT) [2]-[10], DST or inverse discrete sine transform (IDST) [11]-[13], discrete Fourier transform (DFT) [14], or discrete Hartley transform (DHT) [15]-[18]. In this paper we propose an efficient VLSI implementation of both IDCT and IDST based on a modular and regular computational structure called pseudo-band correlation.

It is shown that it is possible to convert the computation of IDCT and IDST in a such computational structure and that can be obtained an efficient unified VLSI implementation with a high percentage of the chip area used by the both transforms. The rest of the paper is organized as follows: in Section II an unified VLSI algorithm based on a pseudo-correlation structure is proposed. In Section III it is presented the unified VLSI architecture

THEUNIFIEDVLSIARCHITECTUREFOR1-DIDCT AND IDST

The hardware core for the proposed unified VLSI architecture for 1D IDCT and IDST is presented in Figure 1(a), whilst in Figure 1(b) there’s reflected the functionality of the processing elements(PE) of the proposed architecture, which has the purpose of selecting addition or subtraction depending on the case which is established by using the control bits dictated by sign. Equation (24) is the one that the hardware core is using for implementation, representing the pseudo-band correlation structure.
 

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On this structure, the transform is mapped on a linear system array.The appropriate reorder of the auxiliary unified input and output sequences are obtained using the pre-processing and post-processing stages. 

The proposed unified algorithm is presented in (19) where in the pre-processing stage we compute the auxiliary input sequence {}1,...,1,0:)(−=NkkYuas shown in equation (26), and for the post-processing stage we recursively compute the auxiliary output sequence {}1,...,1,0:)(−=′Nkkxby using (22) and (23). Equation (20) is the one that aids in controlling the sign of the output sequence. Based on the reformulated computation of 1-D IDST as a pseudo-band correlation used in [13], this paper presents a unified algorithm for IDCT and IDST, thus presenting the advantage of a better performance in digital signal processing applications for high and low correlated images. The IDCT transform can be thus implemented on a similar structure as that used for IDST, both having the same main core and modifications appearing in the pre-processing block.  Code Shoppy

Thus, the advantages include those presented in [13] which are small number of I/O channels located at the 2 extreme ends which aids in obtaining a highly efficient VLSI chip, low hardware costs, a high speed performance with low I/O costs. The unified VLSI architecture is highly regular, modular, with a reduced I/O bandwidth and a minimum hardware modification as both transform can be implemented on the same hardware structure with minimum adjustments.